A typical computer system includes a system clock that is used as a time reference by system components to perform operations. However, computer chips, such as microprocessors, need a time reference, i.e., a core clock signal, that has a significantly greater frequency than that of the system clock because computer chips generally operate at much faster speeds than other system components. In order to generate a core clock signal that has a greater frequency than the system clock, computer systems typically include a clock generator component, such as a phased-lock loop (xe2x80x9cPLLxe2x80x9d).
A PLL, which is often used to control the frequency and/or phase of a signal, is a system that uses feedback to maintain an output signal in a specific phase relationship with a reference signal. The phase relationship between two signals is the amount of phase difference (also referred to as xe2x80x9cphase marginxe2x80x9d) between those two signals. The phase of a signal is the fraction of a period that has elapsed in a periodic function, e.g., a core clock signal, measured from some fixed origin. By maintaining a specific phase relationship, e.g., a phase margin of 0, the core clock signal generated by the PLL can be aligned with the system clock such that the start of a core clock signal cycle occurs at the start of a system clock cycle. Therefore, a functional objective of the PLL is to generate a core clock signal from a system clock and maintain a specific phase difference between the two signals such that the core clock signal generated by the PLL is aligned with the system clock.
FIG. 1 shows a prior art embodiment of a PLL (10). The PLL (10) includes a first buffer (12) that inputs a system clock, SYS_CLK. The first buffer (12) restores SYS_CLK to xe2x80x9cfull swingxe2x80x9d such that any voltage dissipation or stray voltage addition to SYS_CLK present at the input of the first buffer (12) is removed at the output of the first buffer (12). For example, SYS_CLK may be desired to cycle between 0 and 5 volts. However, due to system conditions, e.g., current leakage and/or voltage dissipation, SYS_CLK may only cycle between 0 and 4.5 volts at the input of the first buffer (12). The first buffer (12) then inputs SYS_CLK and restores SYS_CLK such that the first buffer (12) outputs a restored SYS_CLK signal that cycles between 0 and 5 volts.
The PLL (10) also includes a second buffer (14) that inputs a core clock signal, CORE_CLK. The second buffer (14) restores CORE_CLK, in essentially the same manner as the first buffer (12) restores SYS_CLK.
The first buffer (12) outputs the restored (also referred to as xe2x80x9cbufferedxe2x80x9d) SYS_CLK signal to a first clock divider (16) and the second buffer (14) outputs the restored (also referred to as xe2x80x9cbufferedxe2x80x9d) CORE_CLK signal to a second clock divider (18). The first clock divider (16) contains dividers and/or counters that divide SYS_CLK down, i.e., SYS_CLK""s frequency decreases. As opposed to the first clock divider (16), which resides in a feed forward path of the PLL (10), the second clock divider (18) resides in a feedback path of the PLL (10). Accordingly, the second clock divider (18) divides down CORE_CLK. However, those skilled in the art will appreciate that because the second clock divider (18) resides in the feedback path of the PLL (10), the dividing down of CORE_CLK actually results in the multiplying of CORE_CLK, i.e., CORE_CLK""s frequency increases.
The SYS_CLK signal and the CORE_CLK signal generated by the first clock divider (16) and the second clock divider (18), respectively, serve as inputs to a phase-frequency detector (xe2x80x9cPFDxe2x80x9d) (20). The PFD (20) contains a device that produces two output pulses (not shown). The difference in pulse widths between the two output pulses from the PFD (20) is proportional to the phase difference of the two input signals to the PFD (20). The two output pulses produced by the PFD (20) then serve as inputs to a charge pump (xe2x80x9cCPxe2x80x9d) (22). The CP (22), depending on the difference in pulse widths between its inputs, precharges or dumps charge, i.e., outputs voltage, to a capacitor that is used to control a voltage controlled oscillator (xe2x80x9cVCOxe2x80x9d) (24). The VCO (24) is a circuit that produces a signal that has a frequency proportional to an input control voltage. The VCO (24) sets the frequency of the output signal from the VCO (24).
The signal outputted from the VCO (24) serves as an input to a third clock divider (26). The third clock divider (26) functions in the same manner as the first and second clock dividers (16, 18). After dividing down the signal outputted from the VCO (24), the third clock divider (26) outputs a PLL clock signal, PLL_CLK.
PLL_CLK serves as an input to a multiplexor (28). The buffered SYS_CLK signal also serves as an input to the multiplexor (28). Depending on the state of a select input, SEL, the multiplexor (28) outputs the PLL_CLK or the buffered SYS_CLK signal as a multiplexed CORE_CLK signal (also referred to and shown in FIG. 1 as xe2x80x9cCORE_CLK_1xe2x80x9d).
The multiplexed CORE_CLK signal is then buffered by a third buffer (30) and a fourth buffer (32). The fourth buffer (32) outputs the multiplexed/buffered CORE_CLK signal (also referred to and shown in FIG. 1 as xe2x80x9cCORE_CLK_2xe2x80x9d) for use by a computer chip or other system component and the fourth buffer (32) also outputs the multiplexed/buffered CORE_CLK signal to an input of a header stage (34), which is in a feedback path to the input of the PLL (10).
The header stage (34) inputs the multiplexed/buffered CORE_CLK signal and outputs CORE_CLK, which, in turn, serves as the input to the second buffer (14). The function of the PLL (10) from the point when the second buffer (14) inputs CORE_CLK is described above.
One goal of a phased-lock loop and other clock generators is to be able to manipulate a clock cycle in order to find circuit paths that limit peak performance of a certain component. For example, to determine if a certain path on a microprocessor is failing, a PLL can lengthen or shorten the cycle time of a core clock signal while a test is executed.
Manipulating a core clock signal generated by a PLL to have a stretched or shortened clock cycle is done by introducing some phase difference between a system clock signal and a core clock signal. In other words, by not precisely aligning a system clock signal and a core clock signal, the PLL can output a signal that represents an elongated or a shortened signal that is the synthesis of the system clock signal and the core clock signal. Further, the manipulation of the PLL output introduces phase error to the PFD input because the phase difference between the system clock signal and the core clock signal is fed back in the function of the PLL. The dominant resultant phase error, or noise, appears as phase noise (xe2x80x9cjitterxe2x80x9d) on the output signal from the PLL. Moreover, such phase noise can cause the PLL to go out of lock.
In one aspect, a clock multiplexor stage comprises a multiplexor stage that inputs a clock signal at a first input thereof and a delay element that inputs the clock signal and outputs a delayed clock signal to a second input of the multiplexor. Therefrom, a select input on the multiplexor switches between the clock signal and the delayed clock signal to generate a stretched or shortened clock cycle at the output of the multiplexor stage. Those skilled in the art will appreciate that in alternative embodiments, a clock multiplexor stage can output a plurality of clock cycles and/or clock phases that are stretched, shortened, or a combination thereof.
In another aspect, a clock generator comprises a first clock multiplexor stage that inputs a first intermediary clock signal and outputs a first multiplexed clock signal, a second clock multiplexor stage that inputs a second intermediary clock signal and outputs a second multiplexed clock signal, a phase detector stage that inputs the first multiplexed clock signal and the second multiplexed clock signal and outputs an aligned clock signal to a third frequency divider that generates a third clock signal, and a third clock multiplexor stage that inputs the third clock signal and outputs the second clock signal.
In another aspect, a method for stretching and shortening a clock cycle comprises inputting a clock signal to an input of a multiplexor, inputting the clock signal to a first delay element, generating a first delayed clock signal from the first delay element to a second input of the multiplexor, and selectively switching the multiplexor from selecting the clock signal to selecting the first delayed clock signal such that the multiplexor generates a stretched clock cycle on an output of the multiplexor. Those skilled in the art will appreciate that in alternative embodiments, a plurality of clock cycles and/or clock phases can be generated that are stretched, shortened, or a combination thereof.
In another aspect, a method for generating a clock generator signal comprises inputting a first intermediary clock signal to a first clock multiplexor stage that generates a first multiplexed clock signal, wherein the first intermediary clock signal is based on a first clock signal, inputting a second intermediary clock signal to a second clock multiplexor stage that generates a second multiplexed clock signal, wherein the second intermediary clock signal is based on a second clock signal, generating a third clock signal based on phases and frequencies of the first multiplexed clock signal and the second multiplexed clock signal, inputting the third clock signal to a third clock multiplexor stage, and outputting the second clock signal.
In another aspect, a method for removing a clock cycle at an output of a multiplexor stage comprises selectively switching between either a normal clock signal or a delayed clock signal and a grounded signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.